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19-4994; Rev 0; 10/09
KIT ATION EVALU E AILABL AV
76V, APD, Bias Output Stage with Current Monitoring
General Description Features
76V Maximum Boost Voltage Switch FET Current Monitor with a Wide 1A to 2mA Range, Fast 50ns Time Constant, and 10:1 and 5:1 Ratio 2mA Current Clamp with External Shutdown Precision Voltage Feedback Multiple External Filtering Options 3mm x 3mm, 14-Pin TDFN Package with Exposed Pad
DS1842A
The DS1842A integrates the discrete high-voltage components necessary for avalanche photodiode (APD) bias and monitor applications. A switch FET and precision voltage-divider network are used in conjunction with an external DC-DC controller to create a boost DC-DC converter. A current clamp limits current through the APD and also features an external shutdown. The precision voltage-divider network is provided for precise control of the APD bias voltage. The device also includes a dual current mirror to monitor the APD current.
Applications
APD Biasing GPON ONU and OLT
PART DS1842AN+ DS1842AN+T&R
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 14 TDFN-EP* 14 TDFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
Typical Application Circuit
3.3V LX FBIN CBULK DS1842A SW GATE PGND FBOUT R2 CCOMP R COMP COMP D2 CLAMP CURRENT LIMIT MIROUT ROSA MIR1 R1 MIRIN
CURRENT MIRROR
FB
MIR2
EXTERNAL MONITOR
EP GND DS1875
APD TIA
MON3 NOTE: SEE THE LAYOUT CONSIDERATIONS SECTION.
________________________________________________________________ Maxim Integrated Products
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76V, APD, Bias Output Stage with Current Monitoring DS1842A
ABSOLUTE MAXIMUM RATINGS
Voltage Range on GATE and CLAMP Relative to GND...................................................-0.3V to +12V Voltage Range on MIRIN, MIROUT, FBIN MIR1, and MIR2 Relative to GND........................-0.3V to +80V Voltage Range on FBOUT Relative to GND ..........-0.3V to +6.0V Voltage Range on LX Relative to GND...................-0.3V to +85V Operating Junction Temperature Range ...........-40C to +150C Storage Temperature Range .............................-55C to +135C Soldering Temperature ..........................Refer to the IPC JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40C to +85C, unless otherwise noted.)
PARAMETER Switching Frequency FET Capacitance FET Gate Resistance FET On-Resistance GATE Voltage Switching Current LX Voltage LX Leakage CLAMP Voltage CLAMP Threshold Maximum MIROUT Current MIR1 to MIROUT Ratio MIR2 to MIROUT Ratio MIR1, MIR2 Rise Time (20%/80%) Shutdown Temperature Hysteresis Temperature Leakage on GATE and CLAMP Resistor-Divider Ratio (R1/R2) Resistor-Divider Tempco Resistor-Divider End-to-End Resistance RRES TA = +25C, VFBIN = 76V 308 SYMBOL f SW C GATE CLX RG RDSON VGS ILX VLX I IL(LX) VCLAMP VCLT IMIROUT KMIR1 KMIR2 tRC T SHDN THYS IIL KR TA = +25C, VFBIN = 76V CLAMP = low CLAMP = high 15V < VMIRIN < 76V, IMIROUT > 1A 15V < VMIRIN < 76V, IMIROUT > 1A (Note 1) (Note 2) (Note 2) -1 59.5 50 385 481 0.096 0.192 0.100 0.200 30 +150 5 +1 60.25 ppm/C k VGATE = 0V, VLX = 76V -1 0 1.25 1.8 1.8 2.75 Duty cycle = 10%, f SW = 100kHz VGS = 3V, ID = 170mA VGS = 10V, ID = 170mA 0 VGS = 0V, VDS = 25V f SW = 1MHz CONDITIONS MIN 0 40 90 22 1 0.75 2 1.4 11 680 80 +1 11 2.35 3.85 10 0.104 0.208 V mA V A V V mA A A/A A/A ns C C A TYP MAX 1.2 UNITS MHz pF
Note 1: Rising MIROUT transition from 10A to 1mA; VMIRIN = 40V, 2.5k load. Note 2: Not production tested. Guaranteed by design.
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76V, APD, Bias Output Stage with Current Monitoring
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MIRIN CURRENT vs. MIROUT CURRENT (VMIRIN = 40V)
DS1842A toc01
DS1842A
MIRIN CURRENT vs. TEMPERATURE (VMIRIN = 40V, IMIROUT = 250nA)
90 80 MIRIN CURRENT (A) 70 60 50 40 30 20 10
DS1842A toc02
10,000
100
MIRIN CURRENT (A)
1000
100
10 1 10 100 1000 10,000 MIROUT CURRENT (A)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
MIRIN CURRENT vs. TEMPERATURE (VMIRIN = 40V, IMIROUT = 2mA)
DS1842A toc03
MIR ERROR vs. TEMPERATURE (IMIROUT = 1A)
VMIRIN = 40V 1 ERROR (%)
DS1842A toc04
5
2
4 MIRIN CURRENT (mA)
MIR2
3
0 MIR1 -1
2
1
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
-2 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
MIR ERROR vs. TEMPERATURE (IMIROUT = 1mA)
VMIRIN = 40V 1 ERROR (%) ERROR (%)
DS1842A toc05
MIR ERROR vs. MIROUT CURRENT
VMIRIN = 40V 1
DS1842A toc06
2
2
0
0
MIR2 MIR1
MIR2 MIR1
-1
-1
-2 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
-2 1 10 100 1000 10,000 MIROUT CURRENT (A)
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76V, APD, Bias Output Stage with Current Monitoring DS1842A
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MIR ERROR vs. MIRIN VOLTAGE
DS1842A toc07
MIROUT CLAMP CURRENT vs. MIRIN VOLTAGE
3.4 3.3 3.2 IMIROUT (mA) 3.1 3.0 2.9 2.8 2.7 2.6 TA = +85C TA = +25C TA = -40C
DS1842A toc08
2
3.5
1 ERROR (%)
IMIR2 = 1A
IMIR2 = 1mA
0 IMIR1 = 1A IMIR1 = 1mA -1
-2 10 20 30 40 50 60 70 80 MIRIN VOLTAGE (V)
2.5 10 20 30 40 50 60 70 80 MIRIN VOLTAGE (V)
FET ON-RESISTANCE vs. DRAIN CURRENT
DS1842A toc09
FET ON-RESISTANCE vs. TEMPERATURE
ID = 170mA VGS = 2.5V 1.5 VGS = 3.0V VGS = 3.6V
DS1842A toc10
2.0 VGS = 2.5V 1.5 RDSON ()
2.0
1.0
RDSON () 1.0
VGS = 5.0V
0.5
VGS = 3.0V VGS = 3.6V
VGS = 5V VGS = 10V 0.5 100 IDS (mA) 1000 -40 -20 0 20 40 VGS = 10V 60 80 100
0 1 10
TEMPERATURE (C)
RESISTOR-DIVIDER RATIO vs. FBIN VOLTAGE
DS1842A toc11
RESISTOR-DIVIDER RATIO vs. TEMPERATURE
VFBIN = 40V
DS1842A toc12
60.1
60.00
60.0 RATIO (KR)
59.95 RATIO (KR) 10 20 30 40 50 60 70 80
59.9
59.90
59.8
59.85
59.7 FBIN VOLTAGE (V)
59.80 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
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76V, APD, Bias Output Stage with Current Monitoring
Pin Configuration
TOP VIEW
DS1842A MIR1 MIR2 GND FBOUT CLAMP GATE PGND 1 2 3 4 5 6 *EP 7 8 LX DS1842A 14 MIROUT 13 MIRIN 12 FBIN GATE 11 N.C. 10 N.C. 9 N.C. CLAMP PGND CURRENT LIMIT THERMAL SHUTDOWN MIR1 MIR2 FBOUT LX R2 CURRENT MIRROR R1 FBIN MIRIN
Block Diagram
DS1842A
+ TDFN
*EXPOSED PAD.
EP
GND
MIROUT
Pin Description
PIN 1 2 3 4 5 6 7 8 9, 10, 11 12 13 14 -- NAME MIR1 MIR2 GND FBOUT CLAMP GATE PGND LX N.C. FBIN MIRIN MIROUT EP Current Mirror Monitor Output, 10:1 Ratio Current Mirror Monitor Output, 5:1 Ratio Ground Connection for Device. Connect directly to ground plane. Connect GND to PGND at a single point. See the Layout Considerations section for more information. Feedback Output. Resistor-divider output. Clamp Input. Disables the current mirror output (MIROUT). FET Gate Connection Source of Switch FET. Also connect to boost converter's input and output capacitors. Connect PGND to GND at a single point. See the Layout Considerations section for more information. FET Drain Connection. Connect to switching inductor. No Connection Feedback Input. Resistor-divider input. Current Mirror Input Current Mirror Output. Connect to APD bias pin. Exposed Pad. Connect directly to the same ground plane as GND. FUNCTION
Detailed Description
The DS1842A contains discrete high-voltage components required to create an APD bias voltage and to monitor the APD bias current. The device's mirror outputs are a current that is a precise ratio of the output current across a large dynamic range. The mirror response time is fast enough to comply with GPON Rx burst-mode monitoring requirements. The device has a built-in current-limiting feature to protect APDs. The
APD current can also be shut down by CLAMP or thermal shutdown. The internal FET and resistor-divider are used in conjunction with a DC-DC boost controller to precisely create the APD bias voltage.
Current Mirror
The DS1842A has two current mirror outputs. One is a 10:1 mirror connected at MIR1, and the other is a 5:1 mirror connected to MIR2.
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76V, APD, Bias Output Stage with Current Monitoring DS1842A
Thermal Shutdown
MIR1
CLAMP
As a safety feature, the DS1842A has a thermal-shutdown circuit that turns off the MIROUT and MIRIN currents when the internal die temperature exceeds TSHDN. These currents resume after the device has cooled.
Switch FET
REF
The DS1842A switching FET is designed to complement the DS1875 controller's built-in DC-DC boost controller. APD biasing of 16V to 76V can be achieved using the DS1842A.
Figure 1. Current Clamp from Current Feedback
Precision Voltage-Divider
The DS1842A includes a resistor-divider to use as the feedback network for the boost converter. The DS1842A resistor-divider ratio, KR (R1/R2), is tightly controlled, allowing the boost converter output to be set with very high precision. KR can pair with the DS1875's internal DC-DC boost controller. KR can also be easily modified by adding external series/parallel resistors; however, the temperature coefficient of the external resistors must be considered.
The mirror output is typically connected to an ADC using a resistor to convert the mirrored current into a voltage. The resistor to ground should be selected such that the maximum full-scale voltage of the ADC is reached when the maximum mirrored current is reached. For example, if the maximum monitored current through the APD is 2mA with a 1V ADC full scale, and the 10:1 mirror is used, then the correct resistor is approximately 5k. If both MIR1 and MIR2 are connected together, the correct resistor is 1.6k. The mirror response time is dominated by the amount of capacitance placed on the output. For burst-mode Rx systems where the fastest response times are required (approximately a 50ns time constant), a 3.3pF capacitor and external op amp should be used to buffer the signal sent to the ADC. For continuous mode applications, a 10nF capacitor is all that is required on the output.
Applications Information
Layout Considerations
Proper PCB layout helps reduce switching noise in the system. PGND is the connection of the switching FET and thus carries high current pulses. PGND should also be connected to the boost converter's input capacitor and output bulk capacitor. Ensure that the PGND trace is low impedance and able to carry the high current from the FET. To keep the switching noise on PGND isolated from GND, a star ground configuration should be used. PGND and GND should only be connected together at one point on the PCB. This point can be either the ground side of the output bulk capacitor or the common ground point of the PCB. Keeping all PCB traces as short as possible reduces radiated noise, stray capacitance, and trace resistance.
Current Clamp
The DS1842A has a current clamping circuit to protect the APD by limiting the amount of current from MIROUT. There are three methods of current clamping available: 1) Internally Defined Current Limit The device's current clamp circuit automatically clamps the current when it exceeds the maximum MIROUT current. 2) External Shutdown Signal The CLAMP pin can completely shut down the current from MIROUT. The CLAMP pin is active high. 3) Precise Level Set by External Feedback Circuit A feedback circuit is used to control the level applied to the CLAMP pin. Figure 1 shows an example feedback circuit.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 14 TDFN-EP PACKAGE CODE T1433+2 DOCUMENT NO. 21-0137
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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